It is easy to incorporate an exported model into a Platform Architect platform. The SPD export automatically generates a component library, which includes the generated module. This makes the module available within Platform Architect like any other IP library block.
Embedded Software Development
The final phase is the development of the embedded software. This includes implementation of algorithmic tasks as well as writing drivers for the exported SPD models. In case of the transaction-level bus wrapper, the software drivers perform the model's initialization and configuration as well as data flow control and synchronization. To ease the development of these drivers, the SPD model export automatically generates a skeleton for the software driver.
Example: Wireless Platform Design
We applied the proposed flow to an existing and fully verified SPD system: the Decoder Sub-System of the "WCDMA Downlink System" delivered with SPD's 3GPP WCDMA Library. The test case showed us that the described methodology can be performed in a short period of time. It also allowed the system architect to stay focused on important design challenges, rather than keeping busy with detailed modeling. Figure 5 shows the chosen partitioning of the DSP system.
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5. Partitioned Decoder Sub-System of the "WCDMA Downlink System"
The partitioned system included an exported test bench, six hardware-mapped sub-systems, and three software-mapped sub-systems that provide some control-like functionality.
This system was mapped to a virtual hardware platform that consisted of an ARM968E-S processor model (mainly used for data flow control purposes) and elements from CoWare's Generic IP Library (DMA controller, interrupt controller, and a shared memory for the storage of intermediate results). Figure 6 shows a virtual platform in Platform Architect, including the WCDMA Decoder Sub-System at the bottom of the diagram.
The platform used an Open Core Protocol (OCP) Bus interconnect. Other than that, we applied a point-to-point connection between one port of "Testbench" and one port of "Second Interleaver." (Figure 5 shows both blocks. In Figure 6, "Testbench" is shown as a separate block, but "Second Interleaver" is hidden inside the WCDMA Decoder Sub-System.) As the test bench merely delivers test data to the Decoder sub-system, it was appropriate to use an sc_fifo() connection here. By configuring the sc_fifo() connection to model zero latency and by not connecting the corresponding port to a bus, we achieve the intention of a test bench. There is no delay caused by the input data and there is no extra load on the bus. Additionally, this type of connection does not need any extra software drivers on the data flow controlling processor.
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6. Virtual Platform in PA with 3GPP Decoder Sub-System exported from SPD (at the bottom)
During the export of design parameters, we were able to specify whether "Testbench" was a fixed or a random source. We were also able to specify the source file for the fixed signal source.
The platform depicted in Figure 6 was originally designed to model a system performing video/image processing. We added the WCDMA Decoder Sub-System as a sub-system to the platform. Now the platform "receives" the incoming data (as a signal source file for the "Testbench") and decodes them within the rest of the exported SPD models. The decoded data are converted and then displayed and sent to the corresponding module. The output data of the "CRC Fail" port are used to count the erroneous incoming data blocks. The number of these blocks is continuously monitored and updated within a block that was added from SPD's Interactive Simulation Library (ISL).
Figure 7 shows what can be observed during simulation. The lower right shows the "received" and decoded image. Each time new data blocks are received, the corresponding pixels are added to the displayed picture and the block counter is increased within the ISL table above the display.
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7. Screenshot: Simulation of Decoder Sub-System in Demo Platform
Summary
Due to today's increasing complexity of digital signal processing systems, a design flow is needed to efficiently explore hardware solutions, so that the platform can fit the algorithm. The required flow has to be iterative with short design cycles to converge on an optimal solution in an appropriate amount of time. The platform design flow presented in this article meets these requirements.
The proposed design flow is intended to replace the time-consuming and sequential traditional design flow. After the first virtual platform is built, the iterative exploration can be done quickly. Both the hardware designer and the embedded software developer can further use the resulting virtual hardware platform to start their work almost simultaneously. By relaxing the dependencies they had on each other, time-to-market is reduced significantly.
References
1. Tim Kogel, TLM Peripheral Modeling for Platform-Driven ESL Design: Using the SystemC Modeling Library, Technical Paper, March 2006, http://www.coware.com/
About the authors
Bo Wu is a Senior Staff Solution Specialist for DSP Solutions at CoWare Inc. DSP Solutions span the entire range of technologies CoWare offers for modeling, simulation, and implementation of digital signal processing systems. He has over ten years of industrial experience in wireless system design areas and worked for Nortel Networks, AT&T Wireless, and Cadence Design Systems prior to joining CoWare. Bo holds Bachelor and Master degrees from Tsinghua University, Beijing, China, and Ph.D. degree from University of Victoria, BC, Canada. He can be reached at [email protected].
Jens Reinecke is with Electrical Engineering and Information Technology at the RWTH Aachen University, Germany. He is currently working on his Master Thesis at the Institute for Integrated Signal Processing Systems (ISS). Jens is experienced in ESL modeling and MP-SoC design through his studies at the ISS and his internship at CoWare participating in the development of the algorithm-to-platform design flow. He can be reached at [email protected].
