Partitioning
The term "partitioning" describes the process of subdividing a complete system (called a "System View" in SPD) into smaller sub-systems (called "Detail Views" in SPD). Additionally, decisions are made about the upcoming mapping of the algorithm to hardware and software. SPD's Detail Views are the basis for generating DSP hardware peripheral models from SPD models. An example is shown in Figure 3.
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3. Example of an SPD Detail View
Platform Component Generation
A prepared Detail View can be easily exported as a SystemC module and used as a platform component in Platform Architect. During the export, a number of configurable parameters are available, including:
- Export Parameters: These are used to configure the export session itself, e.g. the type of SystemC wrapper that will be generated.
- Design Parameters: These are used to select parameters that will be accessible after the export. Depending on the generated SystemC wrapper, they are provided as constructor arguments and/or as a part of a possible register interface of the wrapper.
- Design Probes: Probes can be attached to any port of a block in a Detail View. They can be used for debugging and verification purposes.
The generated DSP hardware peripheral model contains the highly optimized SPD data flow simulation executable, wrapped into a SystemC transaction level model, compliant with the SystemC Modeling Library (SCML) modelling standard. SPD simulation executables are designed to be used for simulating large DSP systems. As a result, the DSP peripheral model is efficient, even if the designer encapsulates large hierarchical designs.
The "Programmers View Transaction Level Modeling (PV TLM) Bus Wrapper" represents a Programmer's View target peripheral as shown in Figure 4. It offers a memory-mapped register interface. This register interface is based on a SCML memory model. Through this interface, data can be easily read and written. It also allows the designer to control the platform component.
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4. Transaction-level bus wrapper
The automatically generated transaction-level bus wrapper owns two ports:
- A PV Target Port, which is connected to the platform's bus (if necessary, via a transactor) and linked to the wrapper's register interface
- An Interrupt Port, which can be directly connected to an interrupt controller
The automatically generated transaction-level bus wrapper's register interface consists of a set of 32-bit registers. These registers may be subdivided into three categories:
- Control Registers: They provide control of the wrapper. Through these registers, the embedded software developer can configure and control the wrapper and read out information on the module.
- Port Registers: These can be subdivided again into two types for each port of the original SPD model. There are registers for accessing a port's internal data buffer and registers providing information on a port's data type.
- Parameter Registers: These can be used to specify exported design parameters.
Besides the transaction-level bus wrapper, a SystemC FIFO wrapper can be generated separately or mixed with the transaction-level bus wrapper.
