Micro-op Fusion: An Additional Energy-saving Technique
Typical mainstream processors break down x86 program instructions (macro-ops) into small pieces--the internal instructions called "micro-ops"--before sending the instructions down the processor pipeline to be processed.
Micro-op fusion takes macrofusion down another level. In advanced micro-op fusion, the execution core "fuses" common micro-ops derived from the same macro-op. This reduces the number of micro-ops that need to be executed. The result is more efficient scheduling and better performance at lower power. In fact, studies have shown that micro-op fusion can reduce the number of micro-ops handled by the out-of-order logic by more than 10 percent.
Manage Power Intelligently
Power gating is a technique that reduces power consumption, including the runtime power consumption of a processor's execution cores. The technique is used to power up logic subsystems only if and when they are needed.
Power gating has traditionally been challenging for industry because of the energy consumed in powering the subsystem down and ramping it back up for use. Gating has also been challenging because of the need to maintain overall system responsiveness when returning the subsystem to full power.
Advanced power gating in 65-nm CMOS now allows for intelligent, ultra fine-grained logic control of the individual processor logic subsystems. Only those individual subsystems that are currently required are powered on. With a finer granularity of subsystems, power gating also minimizes the number of subsystems that require power.
In addition, some manufacturers, such as Intel, split many buses and arrays, so that the data required in some modes of operation can be put into a low power state when not needed. The result is optimized energy use in a design that delivers more performance per watt without sacrificing responsiveness.
Challenges In Optimizing Cache
One of the major advantages of moving to a 65-nm process is having enough additional transistors to increase resources and/or improve performance in many critical areas. One such area is cache.
When processors have multiple cores, parallelism must be applied at the core level, not just the processor level. This means optimizing the way the execution cores exchange and share data. Without that optimization, multiple cores will introduce data and memory contention--a traditional issue in microarchitecture design.
Industry addresses this challenge by using one L2 cache for each core. It's simple. No core has to fight with other cores for access to its own cache. The problem in this approach is twofold: When two execution cores need the same data, each core must store that data in its own L2 cache, duplicating the work. Also, when one core isn't fully using its cache, other cores cannot access that underutilized cache for other tasks.
