AMD has announced plans to introduce SSE5, an extension of the x86 instruction set that AMD says is designed to let software developers simplify code and achieve greater efficiency for the most performance-hungry applications. Leendert vanDoorn, a Senior Fellow at AMD, discusses the SSE5 extensions in this Dr. Dobb's Q&A.
Introduced in 1999, SSE (short for "Streaming SIMD Extensions") is a SIMD (Single Instruction, Multiple Data) instruction set for the x86 architecture, designed to increase software performance through the use of special instructions that can operate on multiple pieces of data at one time. The SSE5 specification is available at developer.amd.com/SSE5
SSE5 helps maximize the output of each instruction and consolidates code base by introducing functionality previously only found in specialized, high-performance architectures, to the x86 platform:
- 3-Operand Instructions. A computing instruction is executed by applying a mathematical or logical function to operands, or inputs. By increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective instruction. The ability to execute 3-Operand Instructions is currently only possible on certain RISC architectures.
- Fused Multiply Accumulate. The 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The Fused Multiply Accumulate instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications.
