Beware of Those That Claim Linear Performance Increases

Posted by Markus Levy @ 03:36:PM | June 23, 2009

Allow me to begin this blog post with the summary: It really depends on the application.

CoreMark aims at measuring core efficiency, and nothing else. Multiple copies of CoreMark would (assuming decent scheduling by the underlying scheduler or OS) each operate on a single core. There is no interaction between multiple copies of CoreMark, and synchronization only occurs at the end of the run. Thus we would expect execution of multiple copies to simply result in linear speedup -- and indeed the posted scores show linear speedup.

When comparing CoreMark scores, make sure to check the compiler flags and Recently, EEMBC (Embedded Microprocessor Benchmark Consortium) released a 'free' embedded processor benchmark that we call CoreMark. For the sake of completeness (and curiosity) we included capabilities to allow for execution of multiple copies on multiple cores (and in fact it contains 3 common implementations: PThreads, Fork(with shared memory) and Sockets). Someone recently posted E5405 scores that showed a completely linear speedup with 1,2 and 4 cores. How is this possible?

For true analysis of multi-core devices, system factors such as cache coherency and bus arbitration mechanisms also need to be considered, as does the efficiency of synchronization primitives and the underlying scheduler (or OS). While there are other benchmarks out there to challenge multicore platforms (especially in non-embedded systems), the ones from EEMBC are quite useful for testing embedded platforms.

To return to the summary, while it is possible to see linear speedup in real life, most applications and benchmarks that utilize more than one core (and especially more data-intensive apps) will demonstrate a variable decrease in scaling. Of course, if you've been doing multicore system development, you probably have noticed that already.

This Week's Multicore Reading List
MATLAB and Google App Engine
Logging In C++ : Part 2
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A Conversation with BitMagic's Developer
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Real World Parallelism Webinar Series

  • November 17, 2009
    Visual Effects for Animation - presented by DreamWorks Animation
    Speaker: Ron Henderson (Bio)

    Ron Henderson manages the FX Tools group at DreamWorks Animation, where he is responsible for developing physical simulation and procedural modeling tools. These systems have been used for key visual effects in recent films such as Kung Fu Panda and Monsters vs. Aliens (March 2009).

    Prior to joining DreamWorks in 2002 he was a senior scientist at Caltech with a joint appointment to the Applied Math and Aeronautics departments, where he worked on efficient techniques for the direct numerical simulation of fluid turbulence.

    Abstract:
    In this webinar, Ron Henderson will show examples of visual effects, from hair and feathers to smoke and fire, from a variety of DreamWorks Animation feature films. He will discuss in general terms the kinds of techniques used to achieve particular visual effects. Finally, Henderson will show a detailed breakdown of the dam-breaking scene from Madagascar: Escape 2 Africa, demonstrating how different elements of key frame animation, simulation, and rendering are combined in a real production shot.

  • December 1, 2009
    A Quick and Easy Way to Parallelize a Legacy Codebase with Intel® Threading Building Blocks (TBBs)
    Speaker: Bernard Laberge, Avid, Senior Principal Engineer (Bio)

    Bernard Laberge is a senior principal engineer in the video editors division at Avid. During his seven years with the company he has been actively involved in the replacement of the legacy video processing engines used by Avid editors with a common hardware-abstracted, component-based video processing engine currently running on the CPU with SIMD optimized code, GPU, and dedicated hardware.

    Abstract:
    Learn how to overcome the limitations of a thread-based scheduler, including dealing with the absence of recursive parallelism support and the inefficient handling of unbalanced processing load. Bernard Laberge addresses how Avid resolved the expensive refactoring of their thread-based scheduler into a task-based solution by choosing Intel® Threading Building Blocks (TBBs). He explores how Avid was able to easily integrate the Intel TBBs into their video editor applications and more than 5 million lines of code.

  • December 15, 2009
    How to Use Intel® Parallel Studio to Streamline Code Development in a Multicore Environment
    Speaker: Matt Dunbar, Director for Performance Technology, SIMULIA (Bio)

    Matt Dunbar is the director for performance technology at SIMULIA. Since joining the company in 1993, he has worked on parallelization of the Abaqus suite of products, initially for shared memory architectures and more recently for distributed memory architectures. Dunbar has also been intimately involved in selecting both the hardware and software tools used in the development of the Abaqus product line.

    Abstract:
    Resolve elusive, costly multithreading errors quickly and efficiently with Intel® Parallel Studio. While many coding problems that lead to bugs in software applications are typically straightforward logic errors, errors in managing memory and in multithreading code can sometimes take weeks to months to diagnose and fix. Matt Dunbar explores how and why taking advantage of multicore processors through multithreaded code is critical for compute-intensive applications. While spotlighting his work on SIMULIA's Abaqus finite element solver, Dunbar addresses the need for multicore execution and shares his experiences using Intel Parallel Studio to streamline code development in a multicore environment.