April 26, 2006
Power Management for Mobile Devices
Silicon Techniques for Power Management
Halving the supply voltage reduces power dissipation to one fourth (P=V^2/R). But reduced supply voltage coupled with faster clocks produce noise-immunity problems. New techniques are proposed to eliminate these low power-higher clock problems. For example, Texas Instruments recently introduced the advanced very-low-voltage CMOS (AVC) logic family, which operates on supplies of 3.3, 2.5, or 1.8V with propagation delays of approximately 2 nsec. Digital logic blocks continue to function at even lesser voltages reducing overall system power consumption.
Digital designers are already implementing microprocessors in ultra-deep-submicron (130-, 90- and 65-nanometer) processes, where they have found that the thinner oxides and smaller channel lengths yield fast transistors. Likewise, analog baseband and RF designers are following a path of integration to provide a single-chip wireless solution to their end customers. Voltage scaling has not kept up with oxide scaling, however, which has resulted in leaky system solutions--a definite drain on battery lifetime. Fortunately, there are some power-management techniques that can be used to lower power losses in single-chip solutions.
There are three identifiable forms of power supply drain:
In the active mode, the dissipated power is a summation of both static bias current power dissipation and the average of switched or clocked (dynamic) power dissipation. Standby is a low-power state where most, if not all, of the dynamic power dissipation is absent because the clocks have been gated or turned off. In this mode, the magnitude of the static quiescent current dictates battery lifetime. The third form, off-mode power dissipation, is a function of the subthreshold leakage that the transistors in the chip exhibit when the chip is off, but when the input supply is still present.
If ultradeep-submicron CMOS processes were able to handle the higher voltages of the battery (4.3 V to 5.4 V), the off-mode leakage would be negligible because effective channel lengths would be longer and the gate oxides thicker. Likewise, the active power-supply drain would be reduced, because such a process would be slow in terms of frequency, and dynamic power dissipation is a function of capacitance, frequency and input supply. Thus, one needs to address the matter of direct battery hookup of the power-management circuits. The two most commonly used circuits that can accomplish this with some modification are the low dropout regulator (LDO) and the dc/dc buck switching regulator.
Processors are also a key element in Cellular phone SOCs. Processor designers offer a host of power-management features that can be used to optimize power dissipation. For example, several types of wait, idle, standby, and sleep modes suspend processor operation during periods of inactivity. The trade-off is how quickly the processor can resume operation when called back to action. Designers also incorporate automatic power-saving features into their processors' architectures. By gating the clock, CPU designers can reduce the power to even a single register. System power directly relates to CPU clock speed. Many CPUs runs at a variablespeed clock, allowing designers to adjust the frequency for optimal power savings. Some designers use the variable clock speed to dynamically control the clock rate and, therefore, power consumption from software. The program can increase the CPU clock speed when processing demands are high and then throttle back to a lower speed for non-critical tasks. 
Previous Page |
1 Introduction
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2 Silicon Techniques for Power Management
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3 Software Techniques for Power Management
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4 Unified Power Management Architecture
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5 Conclusion
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