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Embedded Systems

H.264 Codec: Video Compression for Consumer Applications


Our technology comes from a thorough, careful analysis of how each coding tool in the H.264 encoder contributes to the video quality as well as the implementation cost in an ASIC environment. Starting from scratch without any bias from pre-existing coding standards such as MPEG-1/2/4, our technology group focused on the best cost-performance advantage for each block in the H.264 encoder. In addition to the video coding algorithm, a highly intelligent TDM-based scheme was adopted to reduce the amount of data traffic required to handle the large amount of video data, thus further reducing power consumption.

Meeting the Physical Requirements
The following is a summary of the architectural decisions that were made to meet our target the physical requirements:

  • The Qpixel H.264 video compression IC was designed to target the portable consumer devices market. It is well understood that the H.264 implementation complexity is almost 10 times as much as MPEG2. To achieve high video quality and simultaneously reduce the system power consumption, we produced a flexible architectures that is power conscious using state of the art design techniques to reduce die size and power consumption while efficiently handling data traffic to minimize the inefficient, power consuming interactions with external memory.
  • The major factor impacting power consumption is the IC clock tree. In order to fully utilize the potential of H.264 encoding tools to achieve high video quality, the clock frequency must be increased to provide more processing power. However running an IC at higher frequencies directly increases dynamic power consumption, so compromises needed to be made in choosing the performance target and power dissipation of the system.
  • To achieve the highest performance with a given power target, the IC was architected so that external memory stall-cycles were minimized and bus arbitration was optimized to yield high data transfer efficiency.
  • In light of the above considerations, two innovative schemes were implemented to reduce external memory data transfers. One is a frame mapping scheme and the other is TDM bus arbitration. TDM arbitration is highly optimized for our video processing pipeline and frame mapping is optimized for the highest DRAM bandwidth. The H.264 compression tools are carefully evaluated and selected for the trade off between video quality and the DRAM bandwidth requirements to meet the low power budget.

Conclusion and the Next Steps

  • Our unique patented and patent-pending video algorithm and architecture made it possible to implement the Qpixel H.264 Main profile codec in a way best suited for video products requiring both low-power and high video quality.
  • In next generation consumer AV products, there is a need for HD (high definition) resolution and quality. We will continue to apply our innovative algorithmic and architectural techniques to offer highly competitive solutions for HD applications.

References

  • JVT-N050d1.doc
  • H.264 / AVC TEXTBOOK, Authored by S. Okubo et al, Impress Limited
  • Development of Video Coding Technology and Future Prospects, T. Chujo, Toshiba Review Vol.60 No.7, 2005
  • A Study for Bit-rate Control of H.264/AVC Coding, Y. Akima, Graduate Paper of Waseda University, 2004

About the authors
Mingning Gu received his Masters Degree in Computer Science from University of Wisconsin, Madison. He has over 13 years of experience in designing ASICs for video processing and compression standards such as MPEG1, MPEG2, and H.264. Mr. Gu is currently the Director of Architecture at Qpixel Technology, where he's heading up all architecture design activities. Prior to Qpixel, Mr. Gu was the Manager of the ASIC team at VWeb, working on MPEG2 ICs.

Yasuhiro Yamada received his Masters Degree in Electrical Engineering from Doshisha University, Kyoto, Japan in 1971. He then joined JVC R&D Laboratory, where he spend most of his time managing the digital audio-visual technology research and development. He was an active member of MPEG Committee during MPEG-1 and MPEG-2 standardization. He retired JVC in 2005 and is currently working at Qpixel Technology Inc. for its technology strategy.

Hitoshi Watanabe received his Bachelor of Engineering degree from Department of Applied Physics, University of Tokyo, Tokyo, Japan in 1990. He then moved to Stanford University and received his Ph.D. degree from Department of Applied Physics in 1999. Following the completion of his research at Stanford, he joined the R&D team of Pulsent corp. His contributions include the development of a proprietary codec based on object-based video compression algorithm, aiming at 2x coding advantage over H.264, object-based coding algorithm, image segmentation/object extraction, and video pre/post processing. After Pulsent, Dr. Watanabe joined Qpixel as a founding member and has been leading a team to develop Qpixel's core H.264 encoder algorithm. Dr. Watanabe holds patents for H.264 as well as object-based video compression algorithm.

All of the authors can be reached at [email protected].


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