A simplified definition of a filter is a function which allows certain frequencies to pass unaltered while reducing or eliminating frequencies in other ranges. Filtering is a very common DSP algorithm implementation. Filters implemented within DSP processors are called digital filters. It is possible to implement digital filters which could be easily implemented with analog circuitry. It is also possible to implement digital filters which would be very difficult or complex to implement in the analog domain. There are many different named digital filter types with different characteristics, complexities and implementations. Two of the most common filter forms are the FIR and IIR filters. The following table presents some essential digital filter definitions and terminology.
| Term | Definition |
|---|---|
| Impulse Response | A digital filter's output sequence after a single cycle impulse (maximum value) input where the impulse is preceded and followed by an infinite number of zero-valued inputs |
| Finite Impulse Response Filter (FIR) | A class of non-recursive digital filters with no internal data feedback paths. An FIR's output values will eventually return to zero after an input impulse. FIR filters are unconditionally stable. |
| Infinite Impulse Response Filter (IIR) | A class of recursive digital filters with internal data feedback paths. An IIR's output values do not ever have to return to zero (theoretically) after an input impulse, however in practice output values do eventually reach negligibly small values. This filter form is prone to instability due to the feedback paths. |
| Filter coefficients | The set of constants (also called tap weights) which are multiplied against filter data values within a filter structure |
| Tap | An operation within a filter structure which multiplies a filter coefficient times a data value. The data value can be a current or delayed input, output or intermediate value. |
| Limit cycle effect | A filter's output will decay down to a specific range and then exhibit continuing oscillation within a limited amplitude range if the filter input is presented non-zero value inputs (excited) followed by a long string of zero-value inputs |
| Filter order | Equal to the number of delayed data values which must be stored in order to calculate a filter's output value. |
| Recursive filter | A filter structure in which feedback takes place and previous input and output samples are used in the calculation of the current filter output value |
In general IIR filters are more susceptible to finite word length effects such as truncation and arithmetic errors since errors in filter calculation recirculate via feedback paths and errors can build up over time. Further, the higher the order of the filter the more it suffers from quantization effects. In fact IIR filters are so sensitive that few are implemented higher than second order. This is why IIR filters are usually realized in combinations of second order filter sections.
An interesting fixed word length effect can occur in a fixed word length implementation of an IIR filter. In an infinite precision IIR filter implementation the output of the filter will decay asymptotically toward zero if a non-zero input is followed by a long string of zeros. For the same filter implemented in a fixed word length DSP implementation with the same input string the output may decay down to a certain magnitude, after which it will exhibit an oscillating output bounded by some small amplitude range. This is referred to as zero-input limit cycle behavior.
Limit cycling behavior is a result of the truncation of the coefficient values implemented within the feedback paths of the filter. Evaluation of this behavior is complex and difficult. Limit cycle effects do not affect FIR filter implementations since FIR filter implementation forms do not contain any feedback paths. FIR filter implementations generally require one MAC operation for each filter tap.
Algorithm Implementation &ndash Scaling Factor Determination
Scaling factors must be chosen carefully. Scaling factor value determination is based on system characteristics including input signal range, intermediate operation groups, and the implemented order of arithmetic operations.
A companion technique which can reduce the amount of scaling required is rearranging the structure of an algorithm's implementation. By choosing to implement a cascaded rather than direct filter form (detailed in advanced texts) the designer has the option of implementing intermediate sub-stage specific scaling. This intermediate scaling often results in smaller sub-stage scaling than would be required for an equivalent direct form filter implementation.
Detailed discussion of analytical and simulation-based algorithm overflow detection and prevention and implementation of data scaling to minimize signal quantization effects caused by truncation are discussed in great detail in various comprehensive DSP texts.
Conclusion
Implementation of DSP algorithms on fixed point DSP processors requires formatting and storing data values and coefficients in signed binary format within finite length registers. The effects of fixed word length numeric calculations and representation are significant sources of inaccuracy and noise in digital systems. The forced quantization of both incoming data and pre-calculated coefficients results in some loss of system accuracy. Internal arithmetic operations also contribute to system accuracy loss. Some of these error sources can be reduced through algorithm implementation analysis and implementation modifications.
While there are some extra implementation and programming efforts which must be made to implement algorithms in fixed point DSPs there are major advantages as well. If a fixed point DSP can do the job and the final product is both high volume and cost sensitive, the use of a lower cost fixed point DSP processor can be justified from an overall system value analysis.
