As for so many things in computing, the term "configurable" is something of a slippery customer, because it means different things to different people. In the case of cores from ARC (www.arc.com), for example, you have the ability to customize the instruction set " and therefore the architecture of the core. By analyzing your source code application(s) using tools from ARC, you can determine which instructions aren't used and remove them from the instruction set and the processor core. Also, you have the ability to add new instructions to the core (this is a tad more complicated).
Another technique is the concept fielded by Tensilica (www.tensilica.com). In this case, you start with a predefined 32-bit post-RISC processing engine called Xtensa that comprises around 25K gates. Next, Tensilica's tools analyze your C/C++ application and evaluate millions of possible processor extensions based on techniques like single-instruction-multiple-data (SIMD) and vector operations, operator fusion, and parallel execution. Once you select the configuration that's best for your particular application, a processor generator outputs the register transfer level (RTL) description for your custom processor along with a custom compiler, assembler, and source-level debugger. A typical customer may end up with 5 or 6 heterogeneous Tensilica cores on their SoC, and some devices (for networking applications) have several hundred such cores.
As an aside, in February 2006, Tensilica started offering a suite of off-the-shelf cores called the "Diamond Standard" family. These are cores that Tensilica have pre-configured to perform a range of CPU and DSP functions extremely efficiently (these cores feature extremely high performance coupled with low power consumption).
And then we have the guys and gals at CoWare (www.coware.com) with their Processor Designer technology, which allows you to create a custom core from the ground up. As opposed to ARC and Tensilica whom we might regard as providing configurable IP, the tools from CoWare should be regarded as being more of an Electronic Design Automation (EDA) approach. In this case, the folks at CoWare have developed a high-level language that is designed to allow you to specify the required functionality of a processor core, including things like the instructions forming the instruction set, register files, execution units, the memory subsystem, and so forth. Using this language, you can define CPU and/or DSP cores with a wide variety of characteristics, such as single instruction multiple data (SIMD) capabilities, very long instruction word (VLIW) superscalar architectures, and so on. Then, once you are ready, you press the "Go" button and Processor Designer generates the register transfer level (RTL) representation used to create your core, along with a custom assembler, C compiler, linker, debugger, and instruction set simulator (ISS).
Another group of folks worth mentioning are the guys and gals at Target Compiler Technologies (www.retarget.com) whose Chess/Checkers technology also allows you to create a custom core from the ground up. Once again, this is more of an EDA approach. Also known as TCT, Target is an interesting company in that they are reputed to have more design wins in this space than any of their competitors, but not many people know about them (apart fromthe folks who are in this arena). An industry expert once told me that this is largely because everyone who works at Target is an engineer with at least five different jobs, and nobody has the time (or inclination) to do any marketing.
Last but not least, we should also note that ARM (www.arm.com) has a product called OptimoDE that can be used to generate specially configured cores. However, these cores are designed to act as slaves (coprocessors); that is; they require a host processor to load their local memories and start them running.
Reconfigurable Processors
The term "reconfigurable computing" means different things to different folks. The best comparison the authors have heard thus far is that of the transporter systems on Star Trek. By this we mean that we all know how these devices are supposed to work and what they do, but we don't have a clue how to build one with the technologies available today.
Similarly, engineers have a vision of the ideal reconfigurable computing scenario, which involves a silicon chip whose function can be reconfigured at the level of individual logic gates (that is, changing an AND gate into an OR gate, for example) and whose connections between gates can be reconfigured on-the-fly without any negative impact with regard to performance or power consumption. In this dream world, it would also be possible to be reconfiguring certain portions of the device while other portions continued to function, thereby allowing new design variations to dynamically evolve in real-time. The problem is that, at this time, we don't have a clue how to build such a device and – even if we did – we don't have the tools required to program one of these little scamps.
OK, back to the real world. One incarnation of reconfigurable computing that can be achieved with today's technologies is known as static reconfiguration. In this case, a programmable device such as an FPGA is first configured to perform a certain task, and is later reconfigured to perform a different task. By comparison, dynamic reconfiguration refers to configuring different portions of a device "on-the-fly" while other portions of the device continue to perform their tasks.
One interesting scenario involves an FPGA containing a number of soft microprocessor and DSP cores, each executing its own local microcode. A special controller block can be used to supply the various processor cores with new microcode as required (this new microcode could be stored in an external memory).
Perhaps the best example of reconfigurable computing to date is provided by Stretch Inc. (www.stretchinc.com), which provides a family of off-the-shelf software-configurable processors. Each of these chips contains two main units: Tensilica's Xtensa core coupled with Stretch's reconfigurable instruction set extension fabric (ISEF), which contains wide register files and lots of computational units (multipliers, adders, and so forth) in a sea of programmable interconnect. Stretch's tools analyze your C/C++ application and generate a corresponding configuration file to program the ISEF to perform specific tasks. The point here is that the ISEF can be reconfigured thousands of times a second so as to tailor it to better serve different portions of the algorithm.
Summary
This paper has really only touched the surface of the state of play in modern computing. In addition to yet more hardware solutions, it is also necessary to consider such things as operating system issues along with the problems of programming, debugging, verifying, and profiling applications.
The point is that there are now a lot of options available to the designers of today's state-of-the-art systems. As usual, system architects have to perform the traditional tradeoff between power, performance, and cost. Ultimately designers have to ask the questions: How much performance do we want? How much do we need? And how much can we afford?
Clive "Max" Maxfield is president of TechBites Interactive, a marketing consultancy firm specializing in high technology. Max is the author and co-author of a number of books, including Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and How Computers Do Math (ISBN: 0471732788) featuring the pedagogical and phantasmagorical virtual DIY Calculator.
Widely regarded as being an expert in all aspects of computing and electronics (at least by his mother), Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way. Max can be reached at [email protected].
